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1 features ? speech circuit with anti-clipping ? tone-ringer interface with dc/dc converter ? speaker amplifier with anti-distortion ? power-supply management (regulated, unregulated) and a special supply for electret microphone ? voice switch ? interface for answering machine and cordless phone applications ? feature phone ? answering machine ? fax machine ? speaker phone ? cordless phone benefits ? no piezoelectric transducer for tone ringing necessary ? complete system integration of analog signal processing on one chip ? very few external components description the programmable telephone audio processor U4091BM-N is a linear integrated cir- cuit for use in feature phones, answering machines and fax machines. it contains the speech circuit, tone-ringer interface with dc/dc converter, sidetone equivalent and ear-protection rectifiers. the circuit is line-powered and contains all components nec- essary for signal amplification and adaptation to the line. the U4091BM-N can also be supplied via an external power supply. an integrated voice switch with loudspeaker amplifier enables hands-free or loudhearing operation. with an anti-feedback function, acoustic feedback during loudhearing can be reduced significantly. the generated supply voltage is suitable for a wide range of peripheral circuits. programmable telephone audio processor U4091BM-N rev. 4666a?cord?02/03
2 U4091BM-N 4666a?cord?02/03 figure 1. block diagram speech circuit voice switch audio amplifier serial bus dtmf tone ringer clock data reset mcu
3 U4091BM-N 4666a?cord?02/03 figure 2. detailed block diagram 5 4 3 d t m f / m e l o d y f i l t e r o f f s e t c a n c e l e r o f f s e t c a n c e l e r a m p b r x l s m i c l r x d t m f a g c o a m r e c a g c i l t x e p o s w i t c h m a t r i x a g c a g a r x s t b a l t x a c l 2 4 3 4 4 1 3 9 a g a t x 4 2 9 3 8 1 7 1 5 1 6 1 2 2 2 2 1 1 9 2 0 4 0 4 1 7 6 1 8 s a c l 1 4 1 3 a f s c o n t r o l b i d i r s e r i a l b u s 1 / 8 / 1 6 / 3 2 d i v . 3 5 3 4 3 7 3 6 3 3 3 1 3 2 2 4 2 5 2 3 2 6 2 8 2 9 2 7 1 1 3 0 3 . 5 8 m h z o s c . m u x a d c r e g p o r p o w e r s u p p l y r i n g i n g p o w e r c o n v e r t e r 1 0 8 v l v r i n g v m i c r e c o 1 m i c o v m p r a s a v m p r f d o l i d e t t x a m i c r o c o p t i o n a l
4 U4091BM-N 4666a?cord?02/03 pin configuration figure 3. pinning sso44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 strc stc sto ampb mico impsw tldt inldt inldr ct bnmt bnmr adin es reset oscout oscin sda scl int txacl mic3 mic2 mic1 reco2 reco1 vl sense vb vmps vmp vmic tsacl vring impa cosc swout sao1 recin amrec tldr sao2 gnd ind u4091bm
5 U4091BM-N 4666a?cord?02/03 pin description pin symbol function 1 recin receive amplifier input (1) 2 txacl time constant adjustment for transmit anti-clipping 3 mic3 microphone input for hands-free operation 4 mic2 input of symmetrical microphone amplifier with high common-mode rejection ratio 5 mic1 input of symmetrical microphone amplifier with high common-mode rejection ratio 6 reco2 output of the receive amplifier 7 reco1 output of the receive amplifier, also used for sidetone network 8ind the internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. a resistor connected to ground may be used to adjust the dc mask. 9 vl positive supply-voltage input to the device in speech mode 10 sense input for sensing the available line current 11 gnd ground, reference point for dc and ac signals 12 vb unstabilized supply voltage for speech network 13 sao2 negative output of speaker amplifier (push-pull only) 14 sao1 positive output of speaker amplifier (single ended and push-pull operation) 15 vmps unregulated supply voltage for the microcontroller (via series regulator to vmp) 16 vmp regulated output voltage for supplying the microcontroller (typically 3.3 v/6 ma in speech mode) 17 vmic reference node for microphone amplifier, supply for electret microphones 18 tsacl time constant for speaker amplifier anti-clipping 19 vring input for ringer supply 20 impa input for adjusting the ringer input impedance 21 cosc 70-khz oscillator for ringing power converter 22 swout output for driving the external switch resistor 23 int interrupt line for serial bus 24 scl clock input for serial bus 25 sda data line for serial bus 26 oscin input for 3.58-mhz oscillator 27 reset reset output for the microcontroller 28 oscout clock output for the microcontroller 29 es input for external supply indication 30 adin input of a/d converter 31 bnmr output of background-noise monitor receive 32 bnmt output of background-noise monitor transmit 33 ct time constant for mode switching of voice switch 34 tldr time constant of receive-level detector 35 inldr input of receive-level detector 36 inldt input of transmit-level detector 37 tldt time constant of transmit-level detector 38 impsw switch for additional line impedance note: 1. the protection device at pin recin is disconnected.
6 U4091BM-N 4666a?cord?02/03 dc line interface and supply-voltage generation the dc line interface consists of an electronic inductance and a dual-port output stage which charges the capacitors at vmps and vb. the value of the equivalent inductance is given by: the U4091BM-N contains two identical series regulators which provide a supply voltage vmp of 3.3 v suitable for a microprocessor. in speech mode, both regulators are active because vmps and vb are charged simultaneously by the dc line interface. the output current is 6 ma. the capacitor at vmps is used to provide the microcomputer with suffi- cient power during long line interruptions. thus, long flash pulses can be bridged or an lcd display can be turned on for more than 2 seconds after going on-hook. when the system is in ringing mode, vb is charged by the on-chip ringing power converter. in this mode, only one regulator is used to supply vmp with maximum 3 ma. supply structure of the chip a main benefit of the u4091bm is the easy implementation of various applications due to the flexible system structure of the chip. possible applications: ? group listening phone ? hands-free phone ? phones which feature ringing with the built-in speaker amplifier ? answering machine with external supply the special supply topology for the various functional blocks is illustrated in figure 4. there are four major supply states: 1. speech condition: in speech condition, the system is supplied by the line current. if the lidet-block detects a line voltage above approximately 2 v, the internal signal vlon is acti- vated. this is detected via the serial bus, all the blocks which are needed have to be switched on via the serial bus. for line voltages below 2 v, the switches remain in quiescent state as shown in the diagram. 2. power down (pulse dialing): when the chip is in power-down mode (bit lomake), e.g., during pulse dialing, all internal blocks are disabled via the serial bus. in this condition, the voltage regulators and their internal band gap are the only active blocks. 39 mico microphone preamplifier output 40 ampb input for playback signal of answering machine 41 amrec output for recording signal of answering machine 42 sto output for connecting the sidetone network 43 stc input for sidetone network 44 strc input for sidetone network pin description pin symbol function note: 1. the protection device at pin recin is disconnected. l 2r sense c ind r dc r 30 r dc r 30 + -------------------------------------------------------------------------------------- - =
7 U4091BM-N 4666a?cord?02/03 3. ringing: during ringing, the supply for the system is fed into vb via the ringing power converter (rpc). normally, the speaker amplifier in single-ended mode is used for ringing. the frequency for the melody is generated by the dtmf/melody generator. 4. external supply: in an answering machine, the chip is powered by an external supply via pin vb. the answering machine connections can be directly made to U4091BM-N. the answering machine is connected to the pin amrec. for the output amrec, an agc function is selectable via the serial bus. the output of the answering machine will be connected to the pin ampb, which is directly connected to the switching matrix. this enables the signal to be switched to every desired output. figure 4. supply generator ringing power converter (rpc) the rpc transforms the input power at vring (high voltage/low current) into an equiv- alent output power at vb (low voltage/high current) which is capable of driving the low- ohmic loudspeaker. the input impedance at vring is adjustable from 3 k to 12 k by rimpa (zring = rimpa/100) and the efficiency of the step-down converter is approxi- mately 65%. ringing frequency detector (rfd) the U4091BM-N provides an output signal for the microcontroller. this output signal is always double the value of the input signal (ringing frequency). it is generated by a cur- rent comparator with hysteresis. the levels for the on-threshold are programmable in 16 steps, the off-level is fixed. every change of the comparator output generates a high level at the interrupt output int. the information can then be read out by means of a serial bus with either normal or fast read mode. the block rfd is always enabled. table 1. threshold level + - - + 3.3 v 5.5 v v mps v mp 5.5 v v 470 300 k - + r 47 220 1 f 10 r sense r ind c v l v b f f f ringth[0:3] v ring 07v 15 22 v step 1 v
8 U4091BM-N 4666a?cord?02/03 clock output divider adjustment the pin oscout is a clock output which is derived from the crystal oscillator. it can be used to drive a micro-controller or another remote component and thereby reduces the number of crystals required. the oscillator frequency can be divided by 1, 8, 16, 32. dur- ing power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus. table 2. clock output serial bus interface the circuit is controlled by an external microcontroller through the serial bus. the serial bus is a bi-directional system consisting of a one-directional clock line (scl) which is always driven by the microcontroller, and a bi-directional data-signal line. it is driven by the microcontroller as well as from the U4091BM-N (see figure 24). the serial bus requires external pull-up resistors as only pull-down transistors (pin sda) are integrated. write the data is a 12-bit word: a0 - a3: address of the destination register (0 to 15) d0 - d7: content of the register the data line must be stable when the clock is high. data must be shifted serially. after 12 clock periods, the write indication is sent. then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high. read there is a normal and a fast-read cycle. in the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. the U4091BM-N drives the data line. the fast read cycle is indicated by a stro be signal. with the following two clocks the U4091BM-N reads out the status bits rfdo and lidet which indicate that a ringing sig- nal or a line signal is present (see figure 5, figure 6 and figure 7). dtmf dialing the dtmf generator sends a multi-frequency signal through the matrix to the line. the signal is the result of the sum of two frequencies and is internally filtered. the frequen- cies are chosen from a low and a high fr equency group. the circuit conforms to the cept recommendation concerning dtmf option. three different levels for the low level group and two different pre-emphasis (2.5 db and 3.5 db) can be chosen by means of the serial bus (rec. t/cf 46-03). attention: in high gain mode distortion can occur, if agatx is high and dc mask is low. clk[0:1] divider frequency 013.58mhz 18447khz 216224khz 332112khz
9 U4091BM-N 4666a?cord?02/03 melody - confidence tone generation melody/confidence tone frequencies are given in table 3. the frequencies are provided at the dtmf input of the switch matrix. a sinusoidal wave, a square wave or a pulsed wave can be se lected by the serial bus. a square signal means the output is half of the frequency cycle high and half low. a pulsed signal means between the high and low phases are high impedance phases of 1/6 of the period. table 3. status of melody generating table 4. dtmf frequencies table 5. dtmf frequencies table 6. dtmff4 in dtmf mode decimal dtmfm[0:2] status 0 000 dtmf generator off 1 001 confidence tone melody on (sinus) 2 010 ringer melody (pulse) 3 011 ringer melody (square signal) 4 100 dtmf (mid level) 5 101 dtmf (low level) 6 110 dtmf (high level) 7 111 ? decimal dtmff[0:1] in dtmf mode frequency error (%) 0 00 697 -0.007 1 01 770 -0.156 2 10 852 0.032 3 11 941 0.316 decimal dtmff[2:3] in dtmf mode frequency error (%) 0 00 1209 -0.110 1 01 1336 0.123 2 10 1477 -0.020 3 11 1633 -0.182 pre-emphasis selection level 02.5db 13.5db
10 U4091BM-N 4666a?cord?02/03 table 7. dtmf and melody frequencies decimal dtmff [0:4] f hz tone/ name error (%) dtmf freq. dtmp freq. key 0 00000 440.0 a 1 -0.008 697 1209 1 1 00001 466.2 b 1 -0.016 770 1209 4 2 00010 493.9 h 1 -0.003 852 1209 7 3 00011 523.2 c 2 0.014 941 1209 * 4 00100 554.4 des 2 0.018 697 1336 2 5 00101 587.3 d 2 -0.023 770 1336 5 6 00110 622.3 es 2 -0.129 852 1336 8 7 00111 659.3 e 2 0.106 941 1336 0 8 01000 698.5 f 2 -0.216 697 1477 3 9 01001 740.0 ges 2 -0.222 770 1477 6 10 01010 784.0 g 2 0.126 852 1477 9 11 01011 830.0 as 2 -0.169 941 1477 # 12 01100 880.0 a 2 0.288 697 1633 a 13 01101 932.3 b 2 -0.014 770 1633 b 14 01110 987.8 h 2 -0.004 852 1633 c 15 01111 1046.5 c 3 -0.335 941 1633 d 16 10000 1108.7 des 3 -0.355 697 1209 1 17 10001 1174.7 d 3 -0.023 770 1209 4 18 10010 1244.5 es 3 -0.129 852 1209 7 19 10011 1318.5 e 3 0.106 941 1209 * 20 10100 1396.9 f 3 -0.214 697 1336 2 21 10101 1480.0 ges 3 -0.222 770 1336 5 22 10110 1568.0 g 3 0.126 852 1336 8 23 10111 1661.2 as 3 -0.241 941 1336 0 24 11000 1760.0 a 3 -0.302 697 1477 3 25 11001 1864.6 b 3 -0.014 770 1477 6 26 11010 1975.5 h 3 0.665 852 1477 9 27 11011 2093.0 c 4 0.367 941 1477 # 28 11100 2217.5 des 4 0.387 697 1633 a 29 11101 2349.3 d 4 0.771 770 1633 b 30 11110 2663.3 --- 852 1633 c 31 11111 2983.0 --- 941 1633 d
11 U4091BM-N 4666a?cord?02/03 figure 5. write cycle figure 6. normal read cycle figure 7. fast read cycle d6 d7 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 r/w=0 clock data from p strobe from p write cycle data clock a3 a2 a1 a0 r/w=1 d7 d6 d5 d4 d3 d2 d1 d0 data from p strobe from p data from u4091b normal read cycle data clock data from u4091b fast read cycle data strobe from p d7=izc d6=ive
12 U4091BM-N 4666a?cord?02/03 table 8. names and functions of the serial registers register group no. name descripion status r0 enables r0b0 enring enable ringer 1 r0b1 erx enable receive part 0 r0b2 etx enable transmit part 0 r0b3 envm enable vm-generator 1 r0b4 enmic enable microphone 0 r0b5 enstbal enable side tone 0 r0b6 mute muting earpiece amplifier 0 r0b7 enrlt enable por low threshold 1 r1 enables r1b0 ensacl enable anti-clipping for speaker amplifier 0 r1b1 ensa enable speaker amplifier and afs 0 r1b2 ensao enable output stage speaker amplifier 0 r1b3 enam enable answering machine connections 0 r1b4 enagc enable agc for answering machine 0 r1b5 free 0 r1b6 free 0 r1b7 foffc speed up offset canceller 0 r2 matrix r2b0 i1o1 switch on mic/ltx 0 r2b1 i1o2 switch on mic/sa 0 r2b2 i1o3 switch on mic/epo 0 r2b3 i1o4 switch on mic/amrec 0 r2b4 i1o5 switch on mic/agci 0 r2b5 i2o1 switch on dtmf/ltx 0 r2b6 i2o2 switch on dtmf/sa 0 r2b7 i2o3 switch on dtmf/epo 0 r3 matrix r3b0 i2o4 switch on dtmf/amrec 0 r3b1 i2o5 switch on dtmf/agci 0 r3b2 i3o1 switch on lrx/ltx 0 r3b3 i3o2 switch on lrx/sa 0 r3b4 i3o3 switch on lrx/epo 0 r3b5 i3o4 switch on lrx/amrec 0 r3b6 i3o5 switch on lrx/agci 0 r3b7 i4o1 switch on ampb/ltx 0 r4 matrix r4b0 i4o2 switch on ampb/sa 0 r4b1 i4o3 switch on ampb/epo 0 r4b2 i4o4 switch on ampb/amrec 0
13 U4091BM-N 4666a?cord?02/03 r4b3 i4o5 switch on ampb/agci 0 r4b4 i5o1 switch on agco/ltx 0 r4b5 i5o2 switch on agco/sa 0 r4b6 i5o3 switch on agco/epo 0 r4b7 i5o4 switch on agco/amrec 0 r5 agatx r5b0 eafs enable afs block 0 miclim r5b1 agatx0 gain transmit aga lsb 0 r5b2 agatx1 gain transmit aga 0 r5b3 agatx2 gain transmit aga msb 0 r5b4 michf select rf-microphone input 0 r5b5 dbm5 maimum. transmit level for anti-clipping 0 r5b6 mic0 gain microphone amplifier lsb 0 r5b7 mic1 gain microphone amplifier msb 0 r6 shut down r6b0 sd shut down 0 sidetone r6b1 free 0 r6b2 sl0 slope adjustment for side tone lsb 0 r6b3 sl1 slope adjustment for side tone msb 0 r6b4 lf0 low frequency adjustment for side tone lsb 0 r6b5 lf1 low frequency adjustment for side tone 0 r6b6 lf2 low frequency adjustment for side tone 0 r6b7 lf3 low frequency adjustment for side tone msb 0 r7 sidetone r7b0 p0 pole adjustment for sidetone lsb 0 agarx r7b1 p1 pole adjustment for side tone 0 r7b2 p2 pole adjustment for side tone 0 r7b3 p3 pole adjustment for side tone 0 r7b4 p4 pole adjustment for side tone msb 0 r7b5 agarx0 gain receive agc lsb 0 r7b6 agarx1 gain receive agc 0 r7b7 agarx2 gain receive agc msb 0 r8 eara r8b0 ea0 gain earpiece amplifier lsb 0 line imp. r8b1 ea1 gain earpiece amplifier 0 r8b2 ea2 gain earpiece amplifier 0 r8b3 ea3 gain earpiece amplifier 0 r8b4 ea4 gain earpiece amplifier msb 0 r8b5 imph line impedance selection (1 = 1 k )0 r8b6 lomake short circuit during pulse dialing 0 table 8. names and functions of the serial registers (continued) register group no. name descripion status
14 U4091BM-N 4666a?cord?02/03 r8b7 aimp switch for additional external line impedance 0 r9 afs r9b0 afs0 afs gain adjustment lsb 0 r9b1 afs1 afs gain adjustment 0 r9b2 afs2 afs gain adjustment 0 r9b3 afs3 afs gain adjustment 0 r9b4 afs4 afs gain adjustment 0 r9b5 afs5 afs gain adjustment msb 0 r9b6 afs4ps enable 4-point sensing 0 r9b7 free 0 r10 sa r10b0 sa0 gain speaker amplifier lsb 0 r10b1 sa1 gain speaker amplifier 0 r10b2 sa2 gain speaker amplifier 0 r10b3 sa3 gain speaker amplifier 0 r10b4 sa4 gain speaker amplifier msb 0 r10b5 se speaker amplifier single-ended mode 0 r10b6 lscur0 speaker amplifier charge-current adjustment lsb 0 r10b7 lscur1 speaker amplifier charge-current adjustment msb 0 r11 adc r11b0 adc0 input selection adc 0 r11b1 adc1 input selection adc 0 r11b2 adc2 input selection adc 0 r11b3 adc3 input selection adc 0 r11b4 nwt network tuning 0 r11b5 soc start of adc conversion 0 r11b6 adcr selection of adc range 0 r11b7 mskit mask for interrupt bits 0 r12 dtmf r12b0 dtmff0 dtmf frequency selection 0 r12b1 dtmff1 dtmf frequency selection 0 r12b2 dtmff2 dtmf frequency selection 0 r12b3 dtmff3 dtmf frequency selection 0 r12b4 dtmff4 dtmf frequency selection 0 r12b5 dtmfm0 generator mode selection 0 r12b6 dtmfm1 generator mode selection 0 r12b7 dtmfm2 generator mode selection 0 r13 clk r13b0 clk0 selection clock frequency for c 0 rth r13b1 clk1 selection clock frequency for c 0 tm r13b2 rth0 ringer threshold adjustment lsb 0 table 8. names and functions of the serial registers (continued) register group no. name descripion status
15 U4091BM-N 4666a?cord?02/03 r13b3 rth1 ringer threshold adjustment 0 r13b4 rth2 ringer threshold adjustment 0 r13b5 rth3 ringer threshold adjustment msb 0 r13b6 tme0 test mode enable (low active) 0 r13b7 tme1 test mode enable (high active) 0 r14 tm r14b0 tme2 test mode enable (high active) 0 clor r14b1 tme3 test mode enable (low active) 0 r14b2 free 0 r14b3 clor0 adjustment for calculated receive log amp lsb 0 r14b4 clor1 adjustment for calculated receive log amp 0 r14b5 clor2 adjustment for calculated receive log amp 0 r14b6 clor3 adjustment for calculated receive log amp 0 r14b7 clor4 adjustment for calculated receive log amp msb 0 r15 clot r15b0 free 0 r15b1 free 0 r15b2 free 0 r15b3 clot0 adjustment for calculated transmit log amp lsb 0 r15b4 clot1 adjustment for calculated transmit log amp 0 r15b5 clot2 adjustment for calculated transmit log amp 0 r15b6 clot3 adjustment for calculated transmit log amp 0 r15b7 clot4 adjustment for calculated transmit log amp msb 0 table 8. names and functions of the serial registers (continued) register group no. name descripion status
16 U4091BM-N 4666a?cord?02/03 power-on reset to avoid undefined states of the system when it is powered on, an internal reset clears the internal registers. the system (U4091BM-N + microcontroller) is woken up by any of the following conditions: ? vmp > 2.75 v and vb > 2.95 v ? and line voltage (vl) ? or ringer (vring) ? or external supply (es) the power-down of the circuit is caused by a shut-down sent by the serial bus (sd = 1), low-voltage reset or by the watchdog function (see figure 9, figure 10 and figure 11). watchdog function to avoid the system operating the microcontroller in a wrong condition, the circuit pro- vides a watchdog function. the watchdog has to be retriggered every second by triggering the serial bus (sending information to the ic or other remote components at the serial bus). if there has been no bus transmission for more than one second, the watchdog initiates a reset. the watchdog provides a reset for the external microcontroller, but does not change the U4091BM-N's registers. acoustic feedback suppression acoustical feedback from the loudspeaker to the hands-free microphone may cause instability of the system. the U4091BM-N has a very efficient feedback-suppression cir- cuit which offers a 4-point- or alternatively a 2-point-signal-sensing topology (see figure 8). two attenuators (txa and sai) reduce the critical loop gain via the serial bus either in the transmit or in the receive path. the overall loop gain remains constant under all operating conditions. the logs produce a logarithmically-compressed signal of the tx- and rx-envelope curve. the afscon block determines whether the tx or the rx signal has to be attenuated. the voice-switch topology can be selected by the serial bus. in 2-point-sensing mode, afscon is controlled directly by the log outputs.
17 U4091BM-N 4666a?cord?02/03 figure 8. basic system configurations figure 9. power-on reset (line) cct ct dtd log calcr afscon sa bnm bnm log calct cbnmr bnmr tldr crlo log log cbnmt bnmt ctlo tldt mico inldt rtu ctu txa micro reco1 inldr cru reco2 rru mode control agatx sto line agarx hv sai line t on t rt lid ivdd oscout vmp reset t rt - t on = 4.5 ms t on = start-up oscillator
18 U4091BM-N 4666a?cord?02/03 figure 10. power-on reset (ringing) figure 11. power-on reset (low voltage reset) dial-tone detector the dial-tone detector is a comparator with one side connected to the speaker amplifier input and the other to vm with a 35-mv offset (see figure 12). if the circuit is in idle mode, and the incoming signal is greater than 35 mv (25 mvrms), the comparator's out- put will change thus disabling the receive idle mode. this circuit prevents the dial tone (which would be considered as continuous noise) from fading away as the circuit would have the tendency to switch to idle mode. by disabling the receive idle mode, the dial tone remains at the normally expected full level. background noise monitors this circuit distinguishes speech (which consists of bursts) from background noise (a relatively constant signal level). there are two background-noise monitors, one for the receive path and the other for the transmit path. the receive background-noise monitor is operated on by the receive level detector, while the transmit background noise moni- tor is operated on by the transmit level detector (see figure 13). they monitor the background noise by storing a dc voltage representative of the respective noise levels in capacitors at cbnmr and cbnmt. the volt ages at these pins have slow rise times (determined by the internal current source and an external c), but fast decay times. if the signal at tldr (or tldt) changes slowly, the voltage at bnmr (or bnmt) will remain more positive than the voltage at the non-inverting input of the monitor's output comparator. when speech is present, the voltage at the non-inverting input of the com- parator will rise more quickly than the voltage at the inverting input (due to the burst characteristic of speech), causing its outpu t to change. this output is sensed by the mode-control block. t rt reset t on oscout vmp ivdd vring vb line lid vmp lvi reset oscout lvi lvr
19 U4091BM-N 4666a?cord?02/03 4-point sensing in 4-point sensing mode, the receive- and the transmit-sensing path include additional clogs (calculated logarithmical amplifiers). the block modecon compares the detector output signals and decides whether receive-, transmit- or idle mode has to be activated. depending on the mode decision, modecon generates a differential voltage to control afscon. the modecon block has seven inputs: ? the output of the transmit log (logt) the comparison of logt, clogr ? the output of the receive clog (clogr) - designated i1 ? the output of the transmit clog (clogt) the comparison of clogt, logr ? the output of the receive log (logr) - designated i2 ? the output of the transmit background-noise monitor (bnmt) - designated i3 ? the output of the receive background-noise monitor (bnmr) - designated i4 ? the output of the dial-tone detector the differential output (afst, afsr) of the block modecon controls afscon. the effect of i1-i4 in table 9. note: x = do not care; y = i3 and i4 are not both noise. table 9. mode decision for signal sensing input output i1 i2 i3 i4 mode ttsxtransmit t r y y change mode r t y y change mode rrxsreceive ttnxidle trnnidle rtnnidle rrxnidle logt > clogr i1 = t logt < clogr i1 = r logr < clogt i2 = t logr > clogt i2 = r bnmt detects speech i3 = s bnmt detects noise i3 = n bnmr detects speech i4 = s bnmr detects noise i4 = n
20 U4091BM-N 4666a?cord?02/03 term definitions 1. transmit means the transmit attenuator is fully on, and the receive attenuator is at maximum attenuation. 2. receive means the receive attenuator is fully on, and the transmit attenuator is at maximum attenuation. 3. in idle mode, the transmit and receive attenuator are at half of their maximum attenuation. ? change mode means both the transmit and receive speech are present in approximately equal levels. the attenuators are quickly switched (30 ms) to the opposite mode until one speech level dominates the other. ? idle means speech has ceased in both transmit and receive paths. the attenuators are then slowly switched (1.5 s) to idle mode. 4. switching to full transmit or receive modes from the idle mode is done at a fast rate (30 ms). summary of truth table 1. the circuit will switch to transmit mode if: ? both transmit level detectors sense higher signal levels than the respective receive level detectors and ? the transmit background-noise monitor indicates the presence of speech 2. the circuit will switch to receive mode if: ? both receive level detectors sense higher signal levels than the respective transmit level detectors, and ? the receive background-noise monitor indicates the presence of speech 3. the circuit will switch to the reverse mode if: ? the level detectors disagree on the relative strengths of the signal levels, and at least one of the background-noise monitors indicates speech. 4. the circuit will switch to idle mode when: ? both speakers are quiet (no speech present), or ? when one speaker speech level is continuously overridden by noise at the other speaker's location the time required to switch the circuit between transmit, receive and idle is determined by internal current sources and the capacitor at pin ct. a diagram of the ct circuitry is shown in figure 14. it operates as follows: ? cct is typically 4.7 f. ? to switch to transmit mode, itx is turned on (irx is off), charging the external capacitor to -240 mv below vm. (an internal clamp prevents further charging of the capacitor.) ? to switch to receive mode, irx is turned on (itx is off), increasing the voltage on the capacitor to +240 mv with respect to vm. ? to switch to reverse mode, the current sources itx, irx are turned off, and the current source ifi is switched on, discharging the capacitor to vm. ? to switch to idle mode, the current sources itx, irx, ifi are turned off, and the current source isi is charging the capacitor to vm.
21 U4091BM-N 4666a?cord?02/03 figure 12. dial tone detector figure 13. background noise monitor figure 14. generation of control voltage (ct) for mode switching - + 35 mv in out to mode control v m i 4 dtd - + 56 k 33 k + - + - 36 mv tldr (tldt) 1 f bnmr (bnmt) v m v b i 4 (i 3 ) 10 m a ct control circuit afs control to attenuators i 1-4 4 dial tone det. v m v m i rx i tx i fi i si 10 m a c ct
22 U4091BM-N 4666a?cord?02/03 figure 15. block diagram hands-free mode U4091BM-N 2-point signal sensing figure 16. block diagram hands-free mode U4091BM-N 4-point signal sensing afs control sa micro line sai log log txa cct ct dtd clogr afs control sa logr txa micro mode control line sai clogt bnmt bnmr logt
23 U4091BM-N 4666a?cord?02/03 analog-to-digital converter adc this circuit is a 7-bit successive approximat ion analog-to-digital converter in switched capacitor technique. an internal band gap circuit generates a 1.25-v reference voltage which is the equivalent of 1 msb. 1lsb = 19.5 mv. the possible input voltage at adin is 0 to 2.48 v. the adc needs an soc (start of conversion) signal. in the high phase of the soc sig- nal, the adc is reset. then, 50 ms after the beginning of the low phase of the soc signal, the adc generates an eoc (end of conversion) signal which indicates that the conversion is finished. the rising edge of eoc generates an interrupt at the int output. the result can be read out by the serial bus. voltages higher than 2.45 v have to be divided. the signal connected to the adc is determined by 4 bits: adc0, adc1, adc2 and adc3. tldr/tldt measuring is possi- ble relative to a preceding reference measurement. the current range of il can be doubled by adcr. if adcr is high, s has the value 0.5, otherwise s = 1. the source impedance at adin must be lower than 250 k . accuracy: 1 lsb + 3% figure 17. timing of adc figure 18. adc input selection soc 50 s eoc adin 0.4 x vb 0.4 x vmps 0.4 x sao1 0.4 x vmp 8 x (tldr-ref) 8 x (tldt-ref) 0.4 x off1 0.4 x off2 0.4 x off3 il x 20mv/(1ma x s) adc msb bit5 bit4 bit3 bit2 bit1 lsb soc eoc
24 U4091BM-N 4666a?cord?02/03 note: d = measured digital word (0 d 127) s = programmable gain 0.5 or 1 vp = peak value of the measured signal table 10. input selection ad converter decimal adc[1:4] symbol value 00000off 1 0001 il i1 = s 127 ma d/128 2 0010 adin extern v2 = 2.5 v d/128 (max. 2.5 v) 3 0011 vb v3 = (2.5 v/0.4) d/128 4 0100 vmps v4 = (2.5 v/0.4) d/128 5 0101 vmp v5 = (2.5 v/0.4) d/128 6 0110 tldr v6 = 8 (vp - ref) d/128 7 0111 tldt v7 = 8 (vp - ref) d/128 81000free 9 1001 sao1 v4 = (2.5 v/0.4) d/128 10 1010 offcan1 atmel?s internal use 11 1011 offcan2 12 1100 offcan3 13 1101 free 14 1110 free 15 1111 free
25 U4091BM-N 4666a?cord?02/03 switch matrix the switch matrix has 5 inputs and 5 outputs. every pair of i/os except agco and agcin can be connected. the inputs and out puts used must be enabled. if 2 or more inputs are switched to an output, the sum of the inputs is available at the output. the inputs mic and lrx have offset cancellers with a 3-db corner frequency of 270 hz. ampb has a 60-k input impedance. the txo output has a digitally-programmable gain stage with a gain of 2, 3 to 9 db depending on agatx0 (lsb), agatx1, agatx2 (msb) and a first order low-pass filter with 0.5 db damping at 3300 hz and 3 db damp- ing at 9450 hz. the outputs rxls, epo and amrec have a gain of 0 db. the offset at the outputs of the matrix is less than 30 mv. if a switch is open, the path has a damping of more than 60 db. figure 19. switch matrix diagram lowpass 2.9 db offset canceller agatx1 amrec epo rxls ltx agatx2 agatx0 txo -10 db sto o1 o2 o3 o4 o5 i5 i4 i3 i2 i1 offset canceller ampb lrx dtmf mic agco agci agc
26 U4091BM-N 4666a?cord?02/03 table 11. bits and corresponding switches register no. name description r2 r2b0 i1o1 switch on mic/ltx r2b1 i1o2 switch on mic/rxls r2b2 i1o3 switch on mic/epo r2b3 i1o4 switch on mic/amrec r2b4 i1o5 switch on mic/agci r2b5 i2o1 switch on dtmf/ltx r2b6 i2o2 switch on dtmf/rxls r2b7 i2o3 switch on dtmf/epo r3 r3b0 i2o4 switch on dtmf/amrec r3b1 i2o5 switch on dtmf/agci r3b2 i3o1 switch on lrx/ltx r3b3 i3o2 switch on lrx/rxls r3b4 i3o3 switch on lrx/epo r3b5 i3o4 switch on lrx/amrec r3b6 i3o5 switch on lrx/agci r3b7 i4o1 switch on ampb/ltx r4 r4b0 i4o2 switch on ampb/rxls r4b1 i4o3 switch on ampb/epo r4b2 i4o4 switch on ampb/amrec r4b3 i4o5 switch on ampb/agci r4b4 i5o1 switch on agco/ltx r4b5 i5o2 switch on agco/rxls r4b6 i5o3 switch on agco/epo r4b7 i5o4 switch on agco/amrec
27 U4091BM-N 4666a?cord?02/03 side tone system figure 20. principle circuit of side tone balancing the side tone balancing (stb) has the task of reducing the cross-talk from ltx (micro- phone) to lrx (earpiece) in the frequency range of 0.3 to 3.4 khz. the ltx signal is converted into a current in the mod block. this current is transformed into a voltage sig- nal (line) by the line impedance zl. the line signal is fed into the summing amplifier diff1 via capacitor ck and attenuator amp1. on the other hand the ltx buffered by stoamp drives an external low-pass filter (rst, cst). the external low-pass filter and the internal stb have the transfer function drawn in the stb box. the amplified stb-output si gnal drives the negative input of the sum- ming block. if both signals at the diff1 block are equal in level and phase, we have good suppression of the ltx signal. in this condition, the frequency and phase response of the stb block will represent the frequency curve on line. in real life the line impedance zl varies strongly for different users. to obtain good sup- pression with one application for all different line impendances, the stb function is programmable. the 3 programmable parameters are: 1. lf (gain at low frequency) lf has 15 programming steps of 0.5 db lf(0) provides -2 db gain, lf(15) provides 5.5 db gain sto_diff(lf) = (-10 db - 2 db + 0.5 db lf + 9 db) lt x -10db lf f p sl g stc strc 0-7db stoamp sto 8.2 k sto cto 33 nf 8db mod recin line -10db amp1 9db sto_diff diff1 amp2 + - agarx ltx lrx ck zl sidetone balancing lf p sl
28 U4091BM-N 4666a?cord?02/03 2. p (the pole position of the low-pass) the p adjustment has 31 steps. p(0) means the lowpass determined by the external application (rst, cst). the internally processed low-pass frequency is fixed by equation: 3. sl (sidetone slope; the pole frequency of the high-pass) the sl has 3 steps. sl(0) is a lower frequency of the high-pass. sl(3) is a higher frequency of the high-pass. with sl, can be influenced the suppression at high frequencies. figure 21. audio frequency signal management U4091BM-N f(p) 1 2 cst rst ------------------------------------------------- 1.122 p = 14578 sidetone balancing dtmf generator offset cancel filter < -24dbm/ -22dbm > offset cancel 0db 0db mic3 handset micro- phone intercom micro- phone 0db ampb answering machine vl line lrx dtmf mic ampb 0db agco rxls epo offset cancel dtmf 30db 12db 7db -48db 6db steps 1db steps 7db 0db and 20db (nwt) 32db -23db -10db -3db ... -10db and 7db (nwt) 1.5db steps 26db -3db and -10db (dtmf) 9db 2db 1db steps 1db steps ltx 0db 0db amrec agci 6db mic1 mic2 sao1 sao2 8db reco1 reco2 mod vl amrec agc dtmf < -34dbm/ -32dbm > st earpiece loud- speaker line answering machine 1db steps switching matrix
29 U4091BM-N 4666a?cord?02/03 absolute maximum ratings parameters symbol value unit line current i l 140 ma dc line voltage v l 12 v maximum input current i ring 15 ma junction temperature t j 125 c ambient temperature t amb -25 to +75 c storage temperature t stg -55 to +150 c total power dissipation, t amb = 60 cp tot 0.9 w thermal resistance parameters symbol value unit junction ambient sso44 r thja 70 k/w electrical characteristics f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit dc characteristics dc voltage drop-over circuit i l = 2 ma i l = 14 ma i l = 60 ma i l = 100 ma v l 4.4 8.6 1.6 4.8 7.2 9.2 5.2 9.8 v v v v transmission amplifier, i l = 14 ma, v mic = 2 mv, micg[0:1] = 2, agatx[0:2] = 7 erx = etx = enmic = enstbal = i1o1 = i3o3 = 1, (g t = 48 db) transmit amplification micg[0:1] = 2 agatx[0:2] = 7 g t 45.3 46.5 47.7 db frequency response due to internal filters i l 14 ma, f = 1 khz to 3.4 khz
g t -1 0 db gain change with current i l = 14 ma to 100 ma
g t 0.5 db gain deviation t amb = -10 c to +60 c
g t 0.5 db cmrr of microphoneamplifier cmrr 60 80 db input resistance of mic amplifier r i 50 k input resistance of mic3 amplifier michf = 1 r i 75 150 300 k gain difference between mic1, mic2 to mic3 michf = 1
g t 0.4 db distortion at line i l 14 ma, v l = 700 mv rms d t 2% maximum output voltage i l 19 ma, d < 5%, v mic = 10 mv ctxa = 1 f, dbm5 = 0 v lmax 1.8 3.0 4.2 dbm dbm5 = 1 v lmax 4.8 6.0 6.6 dbm v mic = 20 mv, micg[0:1] = 3 v micomax -4.2 dbm note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
30 U4091BM-N 4666a?cord?02/03 noise at line phosphometrically weighted i l 14 ma, micg[0:1] = 2 agatx[0:2] = 7 no - 73 - 70 dbmp anti-clipping: attack time release time ctxa = 1 f each 3 db overdrive t a t r 2 80 ms ms gain at low operating current i l = 8 ma, i mp = 1 ma v mic = 0.5 mv i vmic = 300 a g t 45 48 db distortion at low operating current i l = 8 ma, i mp = 1 ma v mic = 5 mv i vmic = 300 a d t 5% receiving amplifier i l = 14 ma, v gen = 300 mv, erx = etx = enmic = enstbal = i1o1 = i3o3 = 1, sl[0:1] = 0, lf[0:3] = 1, p[0:4] = 31, afs[0:5] = 54, agarx[0:2] = 0 adjustment range of receiving gain single ended, i l 14 ma, mute = 1, ea[0:4] = 2 - 31 agarx[0:2] = 0 - 7 g r -19 +17 db receiving amplification differential agarx[0:2] = 0 ea[0:4] = 15 ea[0:4] = 31 g r -1 14.7 0 15.7 1 16.7 db db frequency response i l 14 ma, f = 1 khz to 3.4 khz
g rf -1 0 db gain change with current i l = 14 to 100 ma
g r 0.5 db gain deviation t amb = -10 to +60 c
g r 0.5 db ear protection differential i l 14 ma, v gen = 11 v rms ea[0:4] = 15 ep 3 v rms mute suppression (earpiece disconnect from matrix) i l = 14 ma, i303 = 0
g r 60 db output voltage d < 2% differential i l = 14 ma z ear = 68 nf + 100 ea[0:4] = 11 0.775 v rms maximum output current d < 2% z ear = 100 ea[0:4] = 31 i out 4ma p receiving noise phosphometrically weighted i l = 14 ma z ear = 68 nf + 100 ea[0:4] = 15 - 79 - 76 dbmp side tone suppression z = 600 20 db output resistance each output against gnd ro 10 gain at low operating current (receive only) i l = 6.5 ma, i mp = 1 ma i m = 300 ma v gen = 200 mv ea[0:4] = 21, enmic = etx = i101 = 0 g r -2 0 2 db electrical characteristics (continued) f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
31 U4091BM-N 4666a?cord?02/03 distortion at low operating current i l = 6.5 ma, i mp = 1 ma i m = 300 a, ea[0:4] = 15, enmic = etx = i101 = 0 dr 5 % adjustment step: earpiece amplifier
ea[0:4] = 1 for ea[0:4] = 2 ... 31 0.8 1 1.2 db adjustment step: agarx
agarx[0:2] = 1 0.8 1 1.2 db gain for dtmf signal ampb ? reco1/2 ea[0:4] = 1 -10 db ac impedance imph = 0 imph = 1 z impl z imph 595 980 625 1030 655 1080 dtmf, i l = 14 ma, etx = i201 = 1, agatx[0:2] = 7, dtmfm[0:2] = 4, dtmff[0:4] = 0 dtmf level at line (mid gain) sum level, 600 , dtmfm[0:2] = 4 -5.1 -3.6 -2.1 dbm dtmf level at line (low gain) sum level, 600 , dtmfm[0:2] = 5 -7.6 -6.1 -4.6 dbm dtmf level at line (high gain) sum level, 600 , dtmfm[0:2] = 6 agatx[0:2] = 1 -5.2 -3.7 -2.2 dbm pre-emphasis 600 , dtmff4 = 0 dtmff4 = 1 2 3 2.5 3.5 3 4 dbm dbm speaker amplifier, differential mode ampb sao1/2 ensacl = ensa = ensao = enam = i4o2 = 1, sa[0:4] = 31, erx = etx = enmic = enstbal = i1o1 = i3o3 = 1 minimum line current for operation enam = i4o2 = 0 se = 0, i3o2 = 1 imp 1 ma, v gen = 300 mv i lmin 11 ma gain from ampb to sao v ampb = 3 mv, i l = 15 ma, sa[0:4] = 31 sa[0:4] = 0 g sa 36 37 -5.5 38 db adjustment step speaker amplifier
sa[0:4] = -1 1.15 1.35 1.55 db output power single ended load resistance: r ls = 50 , d < 5% v ampb = 40 mv, se = 1 i l = 15 ma i l = 20 ma p sa p sa 3 7 20 mw mw maximum output power differential load resistance: r l = 50 , d < 5% v ampb = 60 mv, se = 0 v b = 5 v p sa 150 mw output noise (input ampb open) phosphometrically weighted i l > 15 ma n sa 240 mv psoph gain deviation i l = 15 ma t amb = -10 to +60 c
g sa 1 db electrical characteristics (continued) f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
32 U4091BM-N 4666a?cord?02/03 mute suppression i l = 15 ma, v l = 0 dbm, v ampb = 4 mv i4o2 = 0 vsao -56 dbm gain change with current i l = 15 to 100 ma
g sa 1db gain change with frequency i l = 15 ma f = 1 khz to 3.4 khz
g sa -1 0 db attack time of anti-clipping 20 db overdrive t r 2ms release time of anti-clipping t f 170 ms adjustment step of charge current ensao = 0, se = 1
lscur[0:1] = 1 -480 -400 -320 a adjustment step of discharge current ensao = 0, se = 0
lscur[0:1] = 1 320 400 480 a charge current pin sao2 ensao = 0, se = 1 lscur[0:1] = 3 i cha -1.45-1.2-0.95 ma discharge current pin sao2 ensao = 0, se = 0 lscur[0:1] = 3 i dis 0.95 1.2 1.45 ma microphone amplifier, v b = 5 v, v mic = 2 mv, v mic3 = 2 mv, enmic = enam = i1o4 = 1, michf = 0 gain mic amp.: mic1/2 ? amrec micg[0:1] = 0 17.4 18.1 18.8 db micg[0:1] = 1 23.2 23.7 24.6 db micg[0:1] = 2 29.1 29.8 30.5 db micg[0:1] = 3 35.0 35.7 36.4 db mic3 to amrec michf = 1, micg[0:1] = 3 35.0 35.7 36.5 db input suppression: mic3 to mic1/2 micg[0:1] = 0, michf = 0 60 db mic1/2 to mic3 michf = 1 60 db settling time offset-cancellers 5 , foffc = 0 9 12 ms settling time offset-cancellers in speed-up mode 5 , foffc = 1 1.8 2.4 ms agc for answering machine, ampb to amrec, enam = enagc = i4o5 = i5o4 = 1 nominal gain v ampb = 5 mv 23.5 25.5 27.5 db maximum output level v ampb = 50 mv, d< 5% 240 300 360 mvp attack time 20 db overdrive 1 ms release time 45 ms switching matrix, vl = 0, vb = 5 v, enam = i4o4 = 1, v ampb = 0.6 v rms input impedance ampb 50 60 70 k gain ampb to amrec -0.7 -0.3 0.1 db electrical characteristics (continued) f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
33 U4091BM-N 4666a?cord?02/03 maximum input level ampb i4o5 = i5o4 = 1, i4o4 = 0 600 mv maximum output level amrec i4o4 = 1 vb- 600 mv v pp offset i4o4: 1 to 0
v amrec 30 mv mute switching matrix i4o4 = 0 60 db power-on reset vl = 0, v mp = 3.3 v, v b = 5 v, u4091 in power-down mode power-on reset by es vb high, vmp threshold vb = 4 v, es = 4 v, rise vmp until reset goes to low vmp on 2.65 2.75 2.85 v power-on reset by es vmp high, vb threshold vmp = 3 v, es = 4 v, rise vb until reset goes to low vb on 3.2 v low-voltage interrupt vl = 0, v mp = 3.3 v, v b = 0 v vmp decreasing decrease vmp until int returns to high vlvi 2.5 2.6 2.7 v power-off reset vl = 0, v mp = 3.3 v, v b = 0 v low-voltage reset decrease vmp until reset returns to low vlvr 2.35 2.45 2.55 v difference voltage between low- voltage interrupt and reset vlvi - vlvr 100 150 mv logical part v mp = 3.3 v, v b = 5 v output impedance at oscout 0.6 0.9 1.2 k pins scl, sda (input mode) input leakage current low level high level 0 < v i < v mp 0.8 v mp -1 0.2 v mp 1 v v a pins int, sda (output mode) output low (resistance to gnd) 150 230 350 switch for additional impedance (pin impsw) v mp = 3.3 v, v b = 3 v switch-off leakage current 0 < v i < v mp impsw = 0 -0.5 5 a resistance to gnd impsw = 1 50 80 maximum current impsw = 1 -5 5 ma afs (a coustic f eedback s uppression), i l = 14 ma, v gen = 300 mv, erx = etx = enmic = enstbal = i1o1 = i3o3 = 1, sl[0 :1] = 0, lf[0:3] = 1, p[0:4] = 31, agarx[0:2] = 0 adjustment range of attenuation i l 15 ma 0 50 db attenuation of transmit gain i l 15 ma, i inldt = 0 a i inldr = 10 a
g t 47 50 53 db attenuation of speaker amplifier i l 15 ma, i inldt = 10 a i inldr = 0 a g sa 47 50 53 db electrical characteristics (continued) f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
34 U4091BM-N 4666a?cord?02/03 supply voltages, v mic = 25 mv, t amb = - 10 to + 60 c v mp i l = 14 ma, r dc = 680 k i mp = 3 ma v mp 3.1 3.3 3.5 v v mps i l = 100 ma, r dc = inf., i mp = 0 ma v mps 5.5 v v mic i l 14 ma, r dc = 1.3 m i m = 700 a v mic 1.5 4 v v b i b = +20 ma, i l = 0 ma v b 5.5 6.3 v ringing power converter, imp = 1 ma, im = 0 r impa = 500 k ? maximum output power v ring = 20.6 v ensa = ensao = se = 1 p sa 15 mw threshold v ring : high to low 7.4 v low to high, ringth [0:3] = 0 6.0 6.7 7.4 v low to highringth [0:3] = 15 19 21 23 v adjustment steps threshold dringth = 1 0.8 1 1.2 v input impedance v ring = 30 v 4.6 5.8 7.0 k maximum input voltage v ringmax 30 v serial bus scl, sda, as, vmp = 3.3 v, rsda = rscl = rint = 12 k ? input voltage high low sda, scl, int v ibus 3.0 0 v dd 1.5 v v output voltage acknowledge low sda i sda = 3 ma v o 0.4 v clock frequency scl f scl 100 khz rise time sda, scl t r 1s fall time sda, scl t f 300 ns period of scl high low high low t h t l 4.0 4.7 s s setup time start condition data stop condition time space (1) t ssta t sdat t sstop t wsta 4.7 250 4.7 4.7 s ns s s hold time start condition data t hsta t hdat 4.0 0 s s electrical characteristics (continued) f = 1 khz, 0 dbm = 775 mv rms , ivmic = 0.3 ma, imp = 3 ma, r dc = 1.3 m , t amb = 25c, z ear = 68 nf + 100 , rls = 50 , z m = 68 nf, resonator: f = 3.58 mhz, all bits in reset condition, unless otherwise specified. parameters test conditions symbol min. typ. max. unit note: 1. this is a space of time where the bus must be from data transmission and before a new transmission can be started
35 U4091BM-N 4666a?cord?02/03 test circuits figure 22. basic test circuit u 4 0 9 1 b m 1 2 4 4 3 4 5 4 3 4 2 4 1 4 0 6 7 8 9 1 0 3 9 3 8 3 7 3 6 3 5 1 1 1 2 1 3 1 4 1 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 1 6 1 7 1 8 1 9 2 0 2 4 2 3 2 1 2 2 + s i n v 3 . 5 8 m h z + + r c d 5 0 s i n + s i n + v v v a v v v v v 1 0 c i n d p w l p w l
36 U4091BM-N 4666a?cord?02/03 figure 23. test circuit for ringing u 4 0 9 1 b m 1 2 4 4 3 4 5 4 3 4 2 4 1 4 0 6 7 8 9 1 0 3 9 3 8 3 7 3 6 3 5 1 1 1 2 1 3 1 4 1 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 1 6 1 7 1 8 1 9 2 0 2 4 2 3 2 1 2 2 3 . 5 8 m h z + + 5 0 v v p w l p w l v b 6 8 n f b c 5 5 6 s d 1 0 3 a 2 . 2 m h v b
37 U4091BM-N 4666a?cord?02/03 bus timing figure 24. bus timing diagram package information t wsta ps t hsta t l t r sda scl t hdat p t hsta t f t h t ssta t sstop p = stop, s = start t hdat ordering information extended type number package remarks U4091BM-Nfn sso44 tube U4091BM-Nfng3 sso44 taped and reeled t4091n-ddb die die on foil technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
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